The present invention relates to a data processing device and a data processing method, and in particular, relates to the data processing device and data processing method for detecting data errors.
As the characteristic of an ECC (Error Correction Code) with the function of single-bit error correction and double-bit error detection (the so-called SEC-DED (single error correction and double error detection)), it is known that all the 4-or-more even-numbered bit errors cannot be detected and that there is the case in which the 3-or-more odd-numbered bit errors are erroneously recognized as a single-bit error, leading to the erroneous correction of the normal bit (Non Patent Literature 1).
On the other hand, Patent Literature 1 discloses a technology for realizing the error detection of multiple bits (3 or more bits) at a comparatively high rate, in an error detection circuit using an ECC capable of the single error correction and double error detection. This error detection circuit uses the ECC and the count number of “1” appearing in each bit of data, and enables the proper detection of errors, even when the data error cannot be detected successfully only by the check with the use of the ECC.    (Patent Literature 1) Japanese Unexamined Patent Application Publication No. 2005-4288    (Non Patent Literature 1) M. Y. Hsiao; “A Class of Optimal Minimum Odd-weight-column SEC-DED Codes”, IBM Journal of Research and Development, Volume 14, Issue 4, published by IBM, July 1970.